Timing Violations

Professor Ryan Robucci

Finding Slack and Violations

In the applet below, you can control the source and destination register clock buffer delays with your pointer (mouse/finger).
Path Delay visulized with Green lines stemming from the source clock. There are two paths represented, a fast and a slow path, each originating from a source register clocked by the source clock and ending at the data input to a register clocked by the destination clock. The data is drawn as it appears at the input to the destinatiin register, delayed with respect to the the source clock edge.
The setup time before the destination clock edge and the hold time after the destination clock edge are marked with red lines defining a window of time in which no data transistions should occur.
Hold Time Violations are highlighted with Yellow.
Setup Time Violations are highlighted with Magenta.
If you place your pointer in the lower left, both clock delays are small and the clock skew is small.
As you move your pointer upward, the destination register clock buffer delay is increased, which increases clock skew and tends to cause hold time violations (potentially race conditions) since it causes data updates at yhe destination to happen too soon.
As you move your pointer to the right, the source register clock buffer delay is increased, which decreases clock skew and tends to cause setup time violations as it delays the data.

Timing Analysis

Path Delay: let Tpd = (Source Register Clk to Q Delay )+ (Combinatorial Path Progation Delay)
Clock Skew: let Tskew = (Destination Register Clock Buffer Dealy) - (Source Register Clock Buffer Delay)

Without clock skew, a setup time and hold time violation checks are simple.
There can be a setup time violation if the path delay is too large:
Tpd > Clock Period - Destination Register Setup Time Requirement
There can be a hold time violation if the path delay is to short in the next cycle:
Tpd < Destination Register Hold Time Requirement

Setup Time Check

A Setup Time Violation exist if a data transistion happens and the following is true:
    Source Clock Delay + Tpd > Clock Period - Destination Register Setup Time + Destination Register Clock Delay
The slack is defined to be margin we have from the violation, is is computed by simply replacing the comparison with a subtraction:
    Slack = (Clock Period - Destination Register Setup Time + Destination Register Clock Delay) - (Source Register Clock Delay + Tpd )
    Slack = (Clock Period - Destination Register Setup Time + Tskew) - Tpd

Hold Time Check

A Hold Violation exists if a data transistion happens and the following is true:
    Source Resgister Clock Delay + Tpd < Destination Register Hold Time + Destination Register Clock Delay
The slack is defined to be the margin we have from the violation, and is computed simply by replacing the comparison with a subtraction:
    Slack = (Source Resgister Clock Delay + Tpd) - (Destination Register Hold Time + Destination Register Clock Delay)
    Slack = Tpd - Destination Register Hold Time - Tskew

Questions

How does increasing the destination register clock delay affect setup and hold slack?
How does increasing the source register clock delay affect setup and hold slack?
Which path (fast or slow) is more concerning for hold time violation?
Which path (fast or slow) is more concerning for setup time violation?
If there is a hold violation, would increasing or decreasing the path delay help? How might you do that in a circuit?
With your pointer, find a condition with a setup time violation. On a piece of paper find the value of the slack (it should be negative).
With your pointer, find a condition with a hold time violation. On a piece of paper find the value of the slack (it should be negative).
With your pointer, find a condition without a hold time violation. On a piece of paper find the value of the slack (it should be positive).
With your pointer, find a condition without a setup time violation. On a piece of paper find the value of the slack (it should be positive).