Due Sept 16th
wire [3:0] u = 4'bx001; wire [3:0] v = 4'b1x10; wire [3:0] a = u & v; wire [3:0] b = u | v; wire [3:0] c = u ^ v; wire d = &u; wire e = |v; wire [3:0] f = |u;
Results:
a ________________________________
b ________________________________
c ________________________________
d ________________________________
e ________________________________
f ________________________________
(Hint: display statements will print in decimal format, so I’ll assume your answer is base 10, though you can provide your answer in any base as long as you note which base)
module q2(); wire [7:0] a=200; wire [7:0] b=256; wire signed [7:0] c=-1; reg [8:0] u; reg [8:0] v; reg [8:0] w; initial begin u=0; v=0; w=0; #1; $strobe(u); $strobe(v); $strobe(w); $display(u); $display(v); $display(w); u=a+b; v={a+b}; w=a+c; end endmodule
Result:
_____________________ Why?:____________________________________________
_____________________ Why?:___________________________________________
_____________________ Why?:___________________________________________
_____________________ Why?:___________________________________________
_____________________ Why?:___________________________________________
_____________________ Why?:___________________________________________
Code:
initial begin A = 0; B = 1; A <= B; B <= A; end
Results:
A ________________________________
B ________________________________
Code:
initial begin A = 1; B = 0; A = B; B = A; end
Results:
A ________________________________
B ________________________________
wire [3:0] u = 4'b01z0; wire [3:0] v = 4'b101z; wire [3:0] a = u & v; wire [3:0] b = u | v; wire [3:0] c = u ^ v; wire d = &u; wire e = |v; wire [3:0] f = |u;
Results:
a ________________________________
b ________________________________
c ________________________________
d ________________________________
e ________________________________
f ________________________________
$strobe and $display.(I) Code:
module q5i(); reg A,B,C; wire D; assign D = ~B; initial begin A = 1; B = 0; C = 0; $strobe(" s:",A,B,C,D); A <= B; $display("d1:",A,B,C,D); B <= A; $display("d2:",A,B,C,D); A <= C; $display("d3:",A,B,C,D); end endmodule
(II) Code:
module q5ii(); reg A,B,C; wire D= ~B; initial begin A = 1; B = 0; C = 1; $strobe(" s:",A,B,C,D); A = B; $display("d1:",A,B,C,D); B <= A; $display("d2:",A,B,C,D); C <= B; $display("d3:",A,B,C,D); end endmodule
module dfaSsR(data, clk, q, reset_n); input data, clk, reset_n; output reg q; q <= data; endmodule
The follow C code describes a linear feedback shift register and prints the output bit lsb for each iteration. You are asked to implement a similar synthesizable hardware module in Verilog that outputs a “new” lsb from an iteration each clock cycle. Include a synchronous reset signal to initialize the state as done in the following code. However, you must create two separate variations maximally based on procedural code:
(I) one which uses separate procedural blocks for combinatoral and sequential hardware, and
(II) another that uses a single procedural block.
Drawing the circuit may be useful.
//Based on code from https://en.wikipedia.org/wiki/Linear-feedback_shift_register #include <stdint.h> #include <stdio.h> int main(void) { uint16_t start_state = 0xACE1u; /* Any nonzero start state will work. */ uint16_t lfsr = start_state; unsigned period = 0; do { unsigned lsb = lfsr & 1; /* Get LSB (i.e., the output bit). */ printf("%d",lsb); lfsr >>= 1; /* Shift register */ if (lsb) /* If the output bit is 1, apply toggle mask. */ lfsr ^= 0xB400u; ++period; } while (lfsr != start_state); return 0; }
Part A) Provide a Verilog module implemented using procedural code with if-else that implements purely combinarial logic with
| S | R | D | Y |
|---|---|---|---|
| 1 | 1 | X | DC |
| 0 | 1 | X | 0 |
| 1 | 0 | X | 1 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
//provide code below //
Part B) Repeat Part A but using a case-statement based code (choose the most appropriate type of case statement). Specify if your implementation is full-case and if it is parallel case, with explanation.
//provide code below //
Differences to subsequent code are marked with //***
A
module me(x,y,m) input x; output y; input m; wire [1:0] x; reg y; wire [1:0] m; always @ (x,m) begin casez(m) 2'b?0: begin y=&x; end 2'b?1: begin y=|x; end endcase end endmodule
B
module me(x,y,m) input x; output y; input m; wire [1:0] x; reg y; wire [1:0] m; always @ (x,m) begin casez(m) 2'b10: begin //*** y=&x; end 2'b?1: begin //*** y=|x; end endcase end endmodule
C
module me(x,y,m) input x; output y; input m; wire [1:0] x; reg [1:0] y; //*** wire [1:0] m; always @ (x,m) begin casez(m) 2'b?0: begin //*** y[0]=&x; //*** end 2'b?1: begin //*** y[1] =|x; //*** end endcase end endmodule
Provide Edit 1:
module me(x,y,m) input x; output y; input m; wire [1:0] x; reg [1:0] y; wire [1:0] m; always @ (x,m) begin casez(m) 2'b?0: begin y[0]=&x; end 2'b?1: begin y[1] =|x; end endcase end endmodule
Provide Edit 2:
module me(x,y,m) input x; output y; input m; wire [1:0] x; reg [1:0] y; wire [1:0] m; always @ (x,m) begin casez(m) 2'b?0: begin y[0]=&x; end 2'b?1: begin y[1] =|x; end endcase end endmodule
(Line Number Shown)
1: module and4_or4(out_y,out_z,in_x); 2: output out_y,out_z; 3: input [3:0] in_x; 5: and M1(out_y,in_x[3],in_x[2],in_x[1],in_x[0]); 6: or M2(out_z,in_x[3],in_x[2],in_x[1],in_x[0]); 7: endmodule
... wire [3:0] x; wire y,z; ... ________________________________________________ // your code here ...
... wire [3:0] x; wire y,z; ... ________________________________________________ // your code here ...
Let y, a,b,c be wires.
create a continuous assignment of y as a XOR (b AND c );
Using explicit structural code (with instantiated verilog primitives):
//provide code below //
Using implicit structural code (without instantiation):
//provide code below //
module df_behav (data, clk, q, q_n, set_n, reset); input data, clk, set_n, reset; output q, q_n; reg q; assign q_n = ~q; always @(posedge clk) begin if (set_n == 0 ) q <= 1; else if (reset == 1) q <= 0; else q <= data; end //end always endmodule
Examine the following module . Assume it is synthesized to a to a netlist with including adders comparators and inverters each with a propagation delay of 4ns. Furthermore, assume the synthesized sequential units are (1-bit registers) with a clk-to-q time of 5 ns in post-synthesis simulation.
module andor(y, count, clk); input clk; output reg [2:0] count; output reg y; initial count <= 0; always @(count) y = ~count[1]; always @(posedge clk) count <= count + y; endmodule
a) Create a testbench for the module which creates an endlessly repeating clk with 25% duty cycle and period of 20ns (5ns high 15 ns low) that also instantiates the module. Also provide a monitor statement to observe the outputs of the module and the time the changes occur.
b) Assume a post synthesis netlist for the module is used. Draw a timing diagram with count and y
module X(count, clk); input clk; output reg [4:0] count; always @(posedge clk) begin if (count < 0) count <= 20; else count <= count - 1; end endmodule
What is the output of the following code?
module Q16(); reg a, b, c; reg x, y, z; reg clk; initial begin a = 0; b = 0; c = 0; x = 0; y = 0; z = 0; clk = 0; #1; a = 1; x = 1; #1; clk = 1; end always @ (posedge clk ) begin b = a; $display("D1: %b %b %b",a,b,c); $strobe( "S1: %b %b %b",a,b,c); c = b; $display("D2: %b %b %b",a,b,c); $strobe( "S2: %b %b %b",a,b,c); end always @ (posedge clk ) begin y <= x; $display("D3: %b %b %b",x,y,z); $strobe( "S3: %b %b %b",x,y,z); z <= y; $display("D4: %h %h %h",x,y,z); $strobe( "S4: %h %h %h",x,y,z); end endmodule // Q16
module sim(); wire x0, x1,x2; wire y1,y2,y3; assign x0=1'b0; assign x1=1'b1; assign x2=1'bz; and (y1,x0,x2); or (y2,x0,x2); assign y3 = (x2)?(y1):(0); initial begin #0 $display(y1); //Result:______Why?:___________________________ $display(y2); //Result:______Why?:___________________________ $display(y3); //Result:______Why?:___________________________ end endmodule
For the 3 starred lines of code below, choose if wire or reg is correct.
Draw the waveforms x1, x2, and y through 30ns. Annotate times of interest.
`timescale 1ns / 1ps module test_bench(); wire/reg x1,x2; //*** wire/reg y; //*** a_module inst0(y,x1,x2); initial begin x1=1; x2=0; #11 x2=1; #6 x2=0; #1 x2=1; end endmodule module a_module(y,x1,x2); input x1,x2; output wire/reg y; //*** assign #5 y=x1 & x2; //inertial delay endmodule
Draw waveform below:
Time: 0 5 10 15 20 25 30
: 0 1 2 3 4 5 6 9 8 9 0 1 2 3 4 5 6 9 8 9 0 1 2 3 4 5 6 9 8 9 0
x1:
x2:
z :
module registeredMux(output reg [15:0] q, input [15:0] d0, input [15:0] d1, input sel, input clk); always @ ( ) begin: mainBlock end endmodule
Discuss the meaning of the starred (**) line towards defining the behavior of hardware synthesized from the following code when none of rst,down, and up are asserted. What if anything can you say about the hardware that is synthesized when it is included and when it is not?
always@(posedge clk) begin: blockA count <= count_comb; end always@(*) begin: blockB if (rst) begin count_comb = 0; else begin if (up) begin count_comb = count+1; end else if (down) begin count_comb = count-1; end else begin count_comb = 8'bxxxxxxxx; //** end end end
Finish this code so that it matches the behavior of blockB above, use a minimal number of case items:
always@(*) begin:blockC casez ({down,up,rst}) //
In the first module, the intent is to model a combinatorial output Y based on the following sum-of-products Boolean expression: . The second is intending to implement a single register in a design obeying the same Boolean expression.
What is wrong each? State this guidelines/practices not followed, and a code correction, but also explain what effect each mistake has on synthesized hardware and/or simulation (e.g. what could go wrong) if used in a system.
module andor(A, B, C, Y); input A, B, C; output Y; reg Y; always @(*) begin if (A & B) begin Y = 1; end else if (B & ~C) begin Y = 1; end end endmodule
module andor(A, B, C, clk, Q); input A, B, C, clk; output Q; reg Q,QP1,QP2; always @(posedge clk) begin QP1 <= A & B; QP2 <= B & ~C; Q <= QP1 | QP2; end endmodule
module sim(); wire x0, x1,x2; wire y1,y2,y3; assign x0=1'b0; assign x1=1'b1; assign x2=1'bz; and (y1,x0,x2); or (y2,x0,x2); assign y3 = (x2)?(y1):(0); initial begin #0 $display(y1); //Result:__Why?:___________________________ $display(y2); //Result:__Why?:___________________________ $display(y3); //Result:__Why?:___________________________ end endmodule
always @ (posedge clk, posedge rst) begin if (rst) begin max<=0; end else if (d>max) begin max<=d; end end
Draw a representative circuit that does not include a register with an enable (ce) .
Write a Verilog module for a lowercase to uppercase converter, using a case statement. The input should be ASCII lowercase or uppercase letters, and the output should be uppercase letters. Add a default output showing error if an inappropriate input is given. Use $display or $monitor to show characters in your testbench. For lowercase to uppercase conversion assume standard ASCII values. Present commented code, commented testbench code, and simulation results.
Separate the always begin..end block in the following code into two separate procedural blocks, one implementing combinatorial hardware and the other one implementing sequential hardware. Provide the rewritten module in the space below.
module funnyLoadCount(count,loadVal16b,loadEn,clk); input clk; input [7:0] loadVal8b; input loadEn; output reg [7:0] count; always @(posedge clk) begin if (count <= 100) count <= count + 10; else if (count<200) count <= count - 20; else if (count >= 200) count <= 0; if (loadEn) count <= loadVal8b; end endmodule
//provide code below //
Write an arithmetic logic unit with 32-bit signed inputs A and B as well as 2-bit control signal signal select. The module should be implemented with strictly combinatorial logic. Decide the appropriate bit vector length and type for y and be sure your design doesn’t lose any information due to overflow.
| select | Output (y) |
|---|---|
| 0 | A+B |
| 1 | A+1 |
| 2 | max(A,B) ← (YOU must implement max in your code) |
//provide code below //
Repeat, but implement registered-output logic without implying any need for feedback or a clock enable on a register.
//provide code below //
Verilog Arith Write a Verilog model of a circuit that adds three 12 bit twos-complement signed numbers to produce result with minimum appropriate bit-length for the output. Include one bit output indicating overflow/underflow detection. Present commented code, commented testbench code, and simulation results.
(Hint: display statements will print in decimal format, so I’ll assume your answer is base 10, though you can provide your answer in any base as long as you note which base)
module q2(); wire [7:0] a=200; wire [7:0] b=56; wire signed [7:0] c=-1; wire [8:0] u; wire [8:0] v; wire [8:0] w; assign u={a+b}; assign v=a+b; assign w=a+c; initial begin #0 $display(u); //Result:______Why?:___________________________ $display(v); //Result:______Why?:___________________________ $display(w); //Result:______Why?:___________________________ end